Re: Cisco AX.25 support (was: Gracilis card question)
- To: firstname.lastname@example.org (Matti E. Aarnio [OH1MQK])
- Subject: Re: Cisco AX.25 support (was: Gracilis card question)
- From: email@example.com (Alan Cox)
- Date: Wed, 1 Mar 1995 09:42:12 +0000 (GMT)
- Cc: A.Cox@swansea.ac.uk, firstname.lastname@example.org
- In-reply-to: <95Feb28.email@example.com> from "Matti E. Aarn
> Actually I don't believe you can push more than 2Mbps (aggregated)
> thru 68302's serial units.
I was thinking one per channel. I'll check the speed as some stuff we work
with here does 2Mb/second HDLC over WAN links using these chips.
> Those all have internal DMA controllers, so a board with internal
> buffer, or (heaven forbid!) busmaster DMA are possible..
> I do like the internal buffer style :-)
For IP an I/O driven board is probably faster as once you start trying to
be clever and do things like IP checksumming as you read from the board
to limit the memory bandwidth problems on typical motherboards bus mastering
DMA gets in the way. I suppose its ok for sending 8). Perhaps shared memory
for ISA (I seem to remember thats one clock less per word ?)
> Right. Do you have any good references on building PCI boards ?
> Must I call Intel ?
I think so , unless anyone else on the list happens to have half a PCI bus TNC
they were designing.